  LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; 



ENTITY or_bus_4 IS
PORT(
	in0: IN std_logic_vector(7 downto 0);
	in1: IN std_logic_vector(7 downto 0);
	in2: IN std_logic_vector(7 DOWNTO 0);
        in3: IN std_logic_vector(7 DOWNTO 0);
                
	outb : OUT std_logic_vector(7 downto 0)
	);
END;

ARCHITECTURE Eirbot OF or_bus_4 IS

BEGIN


PROCESS(in0, in1, in2, in3)
	VARIABLE i : INTEGER RANGE 0 TO 7;
BEGIN
	FOR i IN 0 TO 7 LOOP
		outb(i) <= in1(i) OR in2(i) OR in3(i);
	END LOOP;
END PROCESS;
END;

